1. Field of the Invention
The invention relates generally to a ferroelectric memory cell array and method of storing data using the same, and more particularly to, a non-volatile ferroelectric memory cell array, which is made of a plurality of ferroelectric memory cells formed of a single transistor, can be applied to a device having MFS (Metal Ferroelectric Semiconductor), MFIS (Metal Ferroelectric Insulator Semiconductor) and MFMIS (Metal Ferroelectric Metal Insulator Semiconductor) structure and can be randomly accessed, and method of storing data using the same.
2. Description of the Prior Art
Generally, a transistor of a MOS structure has a gate insulating film and a gate, which are stacked on a semiconductor substrate, and source and drain where impurity ions are implanted into the semiconductor substrate at both sides of the gate. The gate insulating film usually includes an oxide film (SiO2) and the MOS transistor is driven by a voltage applied to the gate.
On the contrary, a ferroelectric memory cell made of a single transistor uses a ferroelectric such as PZT, SBT and the like as the gate insulating film and writes data depending on the polarity characteristic of the ferroelectric.
A non-volatile ferroelectric memory cell maintains its polarity charge even when a supply of the power is stopped. In other words, data is hold by a hysteresis characteristic between the voltage and the storage charge of the ferroelectric. The non-volatile ferroelectric memory cell may consist of one or two transistors and one or two capacitors, or may consist of only a single transistor as a storage element.
FIG. 1 is a graph showing a chargexe2x80x94voltage hysteresis characteristic of a ferroelectric. When the voltage is 0V, the amount of charge Q may have two different values C and E. Therefore, data of a first state E or a second state C is stored in the ferroelectric memory cell using a characteristic that the polarity stat of the ferroelectric is positioned in a constant direction depending on the voltage applied between thin films.
FIGS. 2a and 2b are a structure for explaining an operating principle of a ferroelectric memory cell made of an N channel single transistor. FIG. 2a illustrates a polarity direction in a state that a positive (+) voltage is applied between a gate 3 and a well formed in a P type substrate 1. At this time, charges are induced on the surface of the substrate 1. FIG. 2b illustrates a polarity direction in a state that a negative (xe2x88x92) voltage is applied between the gate 3 and the well formed in the P type substrate 1. At this time, charges are not induced on the surface of the substrate 1. Reference numeral 2 indicates a ferroelectric film and reference numerals 4 and 5 indicate source and drain, respectively.
FIG. 3a is a circuit diagram showing a memory cell array made of a conventional ferroelectric memory cell formed of a single transistor. A plurality of ferroelectric memory cells M formed on a common well are connected between a plurality of word lines WL1xcx9cWLn and bit lines BL1xcx9cBLm. In other words, gates of the memory cells M1xcx9cMm existing in the same row are connected to the word line WL1. In the same manner, gates of the memory cells Mnxcx9cMn+m existing in an nth row are connected to a word line WLn. Drains of the memory cells M1xcx9cMn existing in the same column are connected to a bit line BL1. In the same manner, drains of the memory cells Mnxcx9cMn+m existing in an m-th column are connected to a bit line BLm. Also, sources of the memory cells existing in respective columns are connected to source lines SL1xcx9cSLn, respectively and the well is connected to a common well line WELL.
For example, in the memory cell array, in order to write data of a first state in a single selected memory cell Mn, the supply power Vdd is applied to the word line WLn and a ground voltage GND is applied to the bit line BL1 and the source line SL1. At this time, in order for not-selected memory cells not to be programmed, the ground voltage GND is applied to remaining word lines WL1xcx9cWLnxe2x88x921 and the supply power Vdd is applied to the source lines SL2xcx9cSLn and the bit lines BL2xcx9cBLm, respectively, as shown in FIG. 3b. 
Meanwhile, in order to write data of a second state in the memory cell, the ground voltage GND must be applied to the gate and the supply power Vdd must be applied to the source, drain and well, respectively. In this case, a bias voltage is applied to the memory cells in the entire arrays since the memory cell could not be individually selected.
Therefore, as the conventional memory cell array is constructed so that a given cell could not be independently selected, a random access operation is not allowed. Also, there occurs a write disturb phenomenon in a not-selected memory cell upon a write operation. For example, if unwanted data is written into a memory cell that was experienced by a drain disturb or data is written into a neighboring memory cell, there occurs a phenomenon that data written into the memory cell that was experienced by the drain disturb are repeatedly changed. Thus, reliability of a device is degraded by the write disturb that destruct thus stored data.
In this reason, a non-volatile memory device using a conventional ferroelectric memory cell array in which each cell is formed of a single transistor has not been commercialized.
The present invention is contrived to solve the problems and an object of the present invention is to provide a ferroelectric memory cell array in which a source of a memory cell is connected to a common source line and a well bias voltage is applied through well lines each connected to wells of each of memory cells, and method of storing data using the same.
In order to accomplish the above object, a ferroelectric memory cell array according to the present invention, is characterized in that it comprises a plurality of word lines located in rows; a plurality of bit lines located in columns; a plurality of memory cells connected between the word lines and the bit lines, in which each of the memory cells is composed of a well formed in a substrate; a thin ferroelectric film formed on the substrate over the well; a gate formed on the thin ferroelectric film; and a source and a drain formed in the well at both sides of the gate, a common source line connected to sources of the memory cells; and a plurality of well lines each connected to corresponding one of wells of the memory cells and electrically isolated from each other.
A method of storing data using a ferroelectric memory cell array according to the present invention is characterized in that the ferroelectric memory cell array comprises a plurality of word lines located in rows; a plurality of bit lines located in columns; a plurality of memory cells connected between the word lines and the bit lines, in which each of the memory cells is composed of a well formed in a substrate; a thin ferroelectric film formed on the substrate over the well; a gate formed on the thin ferroelectric film; and a source and a drain formed in the well at both sides of the gate, a common source line connected to sources of the memory cells; and a plurality of well lines each connected to corresponding one of wells of the memory cells and electrically isolated with each other; and the method comprises the steps of selecting a memory cell by applying a given bias voltage to a selected word line and bit line in order to store data into a selected memory cell of the ferroelectric memory cell array; and writing data into the selected memory cell by means of the difference in the voltage between the selected word line and the well line.
Upon the writing operation, a voltage applied to the selected word line is shifted from the supply power to the ground voltage, and a voltage applied to the well line is shifted from the ground voltage to the supply power and then shifted to the ground voltage.
Upon the writing operation, the supply power is applied to a not-selected word line and the ground voltage is applied to a not-selected well line.
The present invention provides a memory cell array in which a plurality of ferroelectric memory cells formed of a single transistor are connected between a plurality of word lines and bit lines. Data is written into respective memory cells depending on its polarity characteristic and the written data is read by a method using variations in the threshold voltage. More particularly, the present invention allows a random access without disturb by connecting sources of each of the memory cells to a common source line and applying a well bias voltage through well lines each connected to wells of each of the memory cells.